|
Experiment Details, Lab Report Format and Schedule: |
 |
| WEEK |
EXPERIMENT |
LAB
REPORT FORMAT
|
GROUPS
|
| 1. |
1. Introduction
to digital CROs and IC testing |
Available
Here |
C1, C2, C3, C4 |
| 2. |
2. Design and implementation of combinational logic circuits |
Available
Here |
C1, C2, C3, C4 |
| 3. |
3. Realization of truth table using multiplexers |
Available
Here |
C1, C2, C3, C4 |
| 4. |
4. Design and analysis of flip flop's |
Available
Here |
C1, C2, C3, C4 |
| 5. |
5.
Design and implementation of 4 bit arithmetic circuit |
Available
Here |
C1, C2, C3, C4 |
| 6. |
6.
Analysis of Shift Registers |
Available
Here |
C1, C2, C3, C4 |
| 7. |
7. Introduction to FPGA - Simulation using Max+Plus on FLEX
10k |
Available
Here |
C1, C2, C3, C4 |
|
8. |
8.
Design and implementation of sync/asynchronous counters |
Available
Here |
C1, C2, C3, C4 |
|
9. |
9.
Design and implementation of combinational logic circuit using FPGA |
Available
Here |
C1, C2, C3, C4 |
|
10. |
10.
Introduction to VHDL - Combinational circuits |
Available
Here |
C1, C2, C3, C4 |
|
|
|
|
|
| |
Mid-Semester Break |
|
|
| 11. |
11.Design
and analysis of a serial adder |
Available
Here |
C1, C2, C3, C4 |
|
12. |
12. Make-Up Lab Session |
|
|
| |
Lab-Exam and Viva |
|
| |
|