EE 201P

Digital Electronics Laboratory II

 

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Experiment # 9

October 2006

 

I. Objectives

Design and implementation of a combinational logic circuits using FPGAs.

II. Problem Statement

           

           (Problem A is for the students/groups with even bench/table numbers)

A. A committee of four members A, B, C, D votes on a specific task, one vote of each member is weighted by the number of stocks he/she owns assume a vote of yes by member A has a weight of 4 similarly weights associated with a YES vote for  each of B, C, and D are 3,2,1 respectively. Inputs to the logic block are YES or NO of members, and output is sum of weights of these votes represented in binary. The logic circuit should be implemented in the lab..

The required combinational circuit must be designed before arriving in the lab. Only those students who have bought the designed circuit will be allowed for experiments.

 

 (Problem B is for the students/groups with odd bench/table numbers)

 

B. Information transferred in a digital system using a 4-bit code in which 3-bits are information bits and 4th bit is parity check, which is chosen’1’ such that total no of ‘1’s in a word is odd .For instance if the information bits are 101 the check bit is 0 resulting in the word 1010.Design a combinational logic circuit, whose output is ‘1’’ if the word has a single bit in error . The designed logic circuit should be implemented in the lab.

The required combinational circuit must be designed before arriving in the lab. Only those students who have bought the designed circuit will be allowed for experiments.

 

    

III. Components Required

 

        The required circuit(s) should be implemented as per problem statement on the Altera FPGA kit using the Max plus software.

 

IV. Other Pre-Lab Exercises

(a)  In question 2 characterize the class of errors your circuit will detect.   

(b)   Give some details of the cable used to download the circuit from the Max Plus to the board.

(c)    Give three important differences between the MAX and FLEX family of FPGAs.

                 

Please make sure that you have shown the result of your implementation to the lab instructor (or TA) and obtained his/her signature. The two partner's in each group must obtain the signatures and attach with the lab/experiment report.                                                                                                                     

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