I. Objectives

Implement sequential digital circuit using VHDL code using ALTERA MAX II software and synthesize the same.

II. Problem Statement (DownLoad VHDL Introduction)

1. Design a single bit full adder circuit using VHDL. The logic circuit should be implemented in the lab but designed before arriving in the lab.

2. Design a combinational circuit to compute square root of four bit binary numbers. For example if the input (1001) is applied the four bit output should be (0011); input (0110) should deliver output (0010). The designed circuit should round off the output to nearest integer value. Assuming that compliments of all inputs are available, design the circuit before arriving in the lab, and demonstrate its implementation to the available instructor or TA. You should also capture (a) timing diagrams of your simulations and (b) your source code and reproduce it in your lab report.

III. Components Required

The required circuit(s) should be implemented as per problem statement on the ALTERA FPGA kit using the Max plus software.

IV. Other Pre-Lab Exercises

(a)   write a VHDL code for a simple latch and a D flip flop.

(b)   What are concurrent statements (assignments) and sequential statements in VHDL?

(c)   Which additional VHDL statement we have to add if we don't specify an explicit sensitivity list?

(d)    Are different processes concurrent?

(e)    The statements WITHIN a process are concurrent or sequential?

Please make sure that you have shown the result of your implementation to the lab instructor (or TA) and obtained his/her signature. The two partner's in each group must obtain the signatures and attach with the lab/experiment report.

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