State the objectives of the experiments briefly in few sentences.

Briefly discuss about the functioning and problems faced by  D flip flop configuration using NAND gates and the SR flip flop configuration using NAND gates. Briefly detail how the SR flip flop , T flip flop and JK flip flops are realized  using the D flip flop IC and other logic gates. And briefly explain the procedure to such realisation.  This should be at least one  page long.

List the ICs that you have used for realizing the circuit(s). State explicitly  if you used any datasheet from the lab or from manufacturers website. Also mention if you employed any multimeter, LED or resistances.

State the truth table of D flip flop that you constructed using minimum number of NAND gates and SR flip flop using NAND gates. Briefly describe the procedure you used to conclude that the given SR flip flop configuration can achieve edge triggering. Obtain the truth tables of SR flip flop, JK flip flop, T flip flop that are realized with D flip flop and verify the truth tables with original truth tables. Show the full schematic of the implemented circuits and label each gate by its chip number. Make sure to include the pin numbers from the chip to show its all input and output connections.

Discuss the outcome of your implementation for all of the circuits and if your circuit worked in first attempt. List the debugging procedure that you followed to detect and correct the problem.

Discuss your experience with the implementing a D flip flop using minimum number of NAND gates and edge triggered SR flip flop using NAND gates. And also discuss your experience with implementing SR flip flop, JK flip flop, T flip flop using D flip flop and state the differences that you have observed in the functioning of the actual ones and these. State the results of your implementation and whether the objective was met. 

Briefly discuss the solutions to each of the three problems detailed in the pre-lab exercises. This should not be more than two pages.