PUBLICATIONS

Journal Papers

  1. M. Wang, Z. Shao and J. Xue, ``On Reducing Hidden Redundant Memory Accesses for DSP Applications," Accepted in IEEE Transactions on Very Large Scale Integration Systems (TVLSI).

  2. C. Xue, J. Hu, Z. Shao, and E. H.-M. Sha, "Iterational Retiming with Partitioning: Loop Scheduling with Complete Memory Latency Hiding", ACM Transaction on Embedded Computing System (TECS), Vol. 9, Issue 3, pp.1-26, Feb. 2010.

  3. M. Qiu, L. T. Yang, Z. Shao, E. H.-M. Sha, ``Dynamic and Leakage Energy Minimization with Soft Real-Time Loop Scheduling and Voltage Assignment," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 18, Issue 3, pp. 501-504, March 2010.

  4. M. Wang, Y. Wang, D. Liu, Z. Qin, Z. Shao, ``Compiler-Assisted Leakage-Aware Loop Scheduling for Embedded VLIW DSP Processors", Journal of Systems & Software (JSS) (Elsevier), Vol. 83, Issue 5, pp. 772-785, May 2010.

  5. K. Sun, M. Wang, Z. Shao, H. Liu, H. Wei, T. Wang, "Design and Synthesis of A Multiprocessor System-on-Chip Architecture for Real-Time Biomedical Signal Processing in Gamma Cameras", Accepted in Journal of VLSI Signal Processing Systems (Springer).

  6. M. Guo, L. Pan, Y. Yang, M. Wang, Z. Shao, "An Effective State-based Predictive Approach for Leakage Energy Management on Embedded Systems", Journal of Design Automation for Embedded Systems (Springer), Volume 13, Number 4, pp. 311-332, December, 2009.

  7. H. Liu, Z. Shao, M. Wang, J. Du, Z. Jia, “Combining Coarse-Grained Software Pipelining with DVS for Scheduling Real-Time Periodic Dependent Tasks on Multi-Core Embedded Systems”, Journal of VLSI Signal Processing Systems (Springer), Volume 57, Number 2, pp. 249-262, November, 2009

  8. C. Xue, Z. Shao, M. Liu, M. Qiu and E. H.-M. Sha, “Optimizing Nested Loops with Iterational and Instructional Retiming,” Journal of Embedded Computing (JEC) (IOS Press), Volume 3, Number 1, pp. 29-37, Jan. 2009.

  9. M. Qiu, C. Xue, Z. Shao, M. Liu and E. H.-M. Sha, ``Energy Minimization for Heterogeneous Wireless Sensor Networks, " Journal of Embedded Computing (JEC) (IOS Press), Volume 3, Issue 2, pp. 109-117, April 2009.

  10. C. Xue, Z. Jia, Z. Shao, M. Wang and E. H.-M. Sha, ``Optimize Address Assignment with Array and Loop Transformations for Minimizing Schedule Length," IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications (TCAS I), Vol. 55, Issue 1, pp. 379-389, Feb. 2008.  

  11. Z. Shao, M. Wang, Y. Chen, C. Xue, M. Qiu, L. T. Yang, E. H.-M. Sha, “Real-Time Dynamic Voltage Loop Scheduling for Multi-Core Embedded Systems”, IEEE Transactions on Circuits and Systems II (TCAS-II), Vol. 54, No. 5, pp. 445 - 449, May 2007.

  12. C. Xue, Z. Shao, and E. H.-M. Sha, "Maximize Parallelism Minimize Overhead for Nested Loops via Loop Striping", The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (JVLSI), Vol. 47, No. 2, pp. 153 - 167, May 2007.

  13. M. Qiu, Z. Jia, C. Xue, Z. Shao and E. H.-M. Sha, ``Voltage Assignment with Guaranteed Probability Satisfying Timing Constraint for Real-time Multiproceesor DSP," The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (JVLSI), Vol. 46, No. 1, pp. 55-73, Jan. 2007.

  14. Bin Xiao, Jiannong Cao, Zili Shao, Edwin H.-M. Sha, "An Efficient Algorithm for Dynamic Shortest Path Tree Update in Network Routing", Journal of Communications and Networks (JCN - KICS), Volume 9, Number 4, Dec. 2007, Pages 499-510.

  15. Bin Xiao, Jiannong Cao, Zili Shao, Qingfeng Zhuge and Edwin H.-M. Sha, "Analysis and Algorithm Design for the Partition of Large-Scale Adaptive Mobile Wireless Networks", Computer Communications (Elsevier), Volume 30, Issue 8, Pages 1899-1912, June 2007.

  16. Z. Shao, C. Xue, Q. Zhuge, M. Qiu, B. Xiao, and E. H.-M. Sha , “Security Protection and Checking for Embedded System Integration Against Buffer Overflow Attacks via Hardware/Software”,  IEEE Transactions on Computers (TC), vol. 55, no. 4, pp. 443-453, Apr. 2006.

  17. Z. Shao, C. Xue, Q. Zhuge, B. Xiao and E. H.-M. Sha, “Loop Scheduling with Timing and Switching-Activity Minimization for VLIW DSP”,  ACM Transactions on Design Automation of Electronic Systems(TODAES), vol. 11, no. 1, pp. 165-185, Jan. 2006.

  18. Q. Zhuge, C. Xue, Z. Shao, M. Liu, M. Qiu and E. H.-M. Sha, “Design Optimization and Space Minimization Considering Timing and Code Size via Retiming and Unfolding,”  Journal of Microprocessors and Microsystems (JMM), Vol. 30, Issue 4,  pp. 173-183, June 2006 (Elsevier)

  19. Z. Shao, Q. Zhuge, M. Liu, C. Xue, E. H.-M. Sha and B. Xiao, “Algorithms and Analysis of Scheduling for Loops with Minimum Switching”, International Journal of Computational Science and Engineering (IJCSE), Vol. 2, pp. 88-97, 2006 (Inderscience).

  20. Z. Shao , J. Cao, K. C. C. Chan, C. Xue , and E. H.-M. Sha, “Hardware/software Optimization for Array & pointer Bound Checking Against Buffer Overflow Attacks”,  Journal of Parallel and Distributed Computing (JPDC), special issue on Security in Grid and Distributed Systems, Volume 66, Issue 9, Pages 1129-1136, September 2006 (Elsevier).

  21. C. Xue, Z. Shao, Q. Zhuge, B. Xiao, M. Liu, and E. H.-M. Sha, “Optimizing Address Assignment for Scheduling DSPs with Multiple Functional Units,” IEEE Transactions on Circuits and Systems II (TCAS-II), Vol. 53, No. 9, pp. 976 - 980, September 2006.

  22. Z. Shao, Q. Zhuge, C. Xue and E. H.-M. Sha, “Efficient Assignment and Scheduling for Heterogeneous DSP Systems”, in IEEE Transaction on Parallel and Distributed Systems (TPDS), pp. 516-525, Vol. 16, No. 6, June, 2005.

  23. Z. Shao, Q. Zhuge, Y. Zhang and E. H.-M. Sha, “Algorithms and Analysis of Scheduling for Low-Power High-Performance DSP on VLIW Processors,”  in International Journal of High Performance Computing and Networking (IJHCN),Vol 1, pp. 3-16, 2004 (Inderscience).

Conference Papers

  1. Y. Wang, D. Liu, M. Wang, Z. Qin, Z. Shao, "Optimal Task Scheduling by Removing Inter-core Communication Overhead for Streaming Applications on MPSoC", in the 16th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2010) in conjunction with CPS Week 2010, Stockholm, Sweden, April 12-16, 2010.

  2. Y. Wang, D. Liu, M. Wang, Z. Qin, Z. Shao, Y. Guan, "RNFTL: A Reuse-Aware NAND Flash Translation Layer for Flash Memory", in ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems (LCTES-2010) in conjunction with CPS Week 2010, Stockholm, Sweden, April 12-16, 2010.

  3. D. Liu, Z. Shao, M. Wang, M. Guo, J. Xue, "Optimal Loop Parallelization for Maximizing Iteration-Level Parallelism", in International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2009), Grenoble, France, Oct. 2009.

  4. M. Wang, D. Liu, Y. Wang, Z. Shao, "Loop Scheduling with Memory Access Reduction under Register Constraints for DSP Applications", in the 2009 IEEE Workshop on Signal Processing (SiPS 2009), Tampere, Finland, Oct. 2009.

  5. M. Wang, Y. Wang, D. Liu, Z. Shao, "Improving the Reliability of Embedded Systems with Cache and SPM", in the 2009 IEEE International Symposium on Trust, Security and Privacy for Pervasive Applications (TSP-09) in conjunction with the 2009 IEEE International Conference on Mobile Ad-hoc and Sensor Systems (IEEE MASS 2009), Macau SAR, China, Oct. 2009.

  6. Y. Yang, M. Wang, Z. Shao, M. Guo, "Dynamic Scratch-pad Memory Management with Data Pipelining for Embedded Systems", in 7th IEEE/IFIP International Conference on Embedded and Ubiqutious Computing (EUC-09), Vancouver, Canada, Aug. 2009.

  7. C. Xue, G Xing, Z Yuan, Z. Shao and E. H.-M. Sha, ``Joint Sleep Scheduling and Mode Assignment in Wireless Cyber-Physical Systems," in The 2nd International Workshop on Cyber-Physical Systems (WCPS 2009) in Conjunction with the 29th International Conference on Distributed Computing Systems (ICDCS 2009) Montreal, Canada, June 2009.

  8. Y. Cao, Z. Shao, M. Wang, C. Xue, Y. Chen, H. Wei, T. Wang, “A Formal Specification and Verification Framework for Designing and Verifying Reliable and Dependable Software for Computerized Numerical Control (CNC) Systems”, in Proc. The 28th International Conference on Distributed Computing Systems (ICDCS 2008), pp. 269-276, June 2008.

  9. H. Liu, Z. Shao, M. Wang, P. Chen, "Overhead-Aware System-Level Joint Energy and Performance Optimization for Streaming Applications on Multiprocessor Systems-on-Chip", in the 20th Euromicro Conference on Real-Time Systems (ECRTS 08), pp. 92-101, June 2008.

  10. B. Zhao, M. Wang, Z. Shao, J. Cao, K. C. C. Chan, J. Su, “Topology Aware Task Allocation and Scheduling for Real-time Data Fusion applications in Networked Embedded Sensor Systems”, in the 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2008), pp. 293-302, Taiwan, Aug. 2008.

  11. C. Xue, Z. Yuan, G. Xing, Z. Shao, and E. H.-M. Sha, "Energy Efficient Operating Mode Assignment for Real-Time Tasks in Wireless Embedded Systems", in The 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp. 237-246, Taiwan, Aug 2008.

  12. M. Wang, Z. Shao, H. Liu, C. Xue, "Minimizing Leakage Energy with Modulo Scheduling  for VLIW DSP Processors", in IFIP Working Conference on Distributed and Parallel Embedded Systems (DIPES 2008), pp. 111-120, Milano, Italy, Sept. 2008.

  13. B. Zhao, M. Wang, Z. Shao, J. Cao, K. C. C. Chan, J. Su, "Topology-Aware Energy-Efficient Task Assignment for Collaborative In-Network Processing in Distributed Networked Sensor Systems", in IFIP Working Conference on Distributed and Parallel Embedded Systems (DIPES 2008),  pp. 201-211, Milano, Italy, Sept. 2008.

  14. L. Pan, Y. Yang, M. Wang, Z. Shao, "A State-based Predictive Approach for Leakage Reduction of Functional Units", The 2008 IEEE/IFIP International Conference On Embedded and Ubiquitous Computing (EUC 2008), Shanghai, China, Dec. 2008.

  15. Y. Yang, Z. Shao, L. Pan, M. Guo, " ISOS: Space Overlapping Based on Iteration Access Patterns for Dynamic Scratch-pad Memory Management in Embedded Systems", Accepted in The 9th International Conference for Young Computer Scientists, China, Nov. 2008. (The best paper award).

  16. C. Xue, E. H.-M. Sha, Z. Shao and M. Qiu, "Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints" Accepted in Proc. IEEE/ACM Design, Automation and Test in Europe (DATE 2008) , pp. 1202-1207, Munich, Germany, March 10-14, 2008.

  17. C. Xue, T. Liu, Z. Shao, J. Hu, Z. Jia, E. H.-M. Sha, ``Address Assignment Sensitive Variable Partitioning and Scheduling for DSPs with Multiple Memory Banks," in Proc. The 33rd IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 08), pp. 1453-1456, Las Vegas, USA, March, 2008.                                     

  18. B. Wang, T. Wang, H. Wei, M. Wang, Z. Shao, “Power-Aware Real-Time Task Scheduling With Feedback Control for Mobile Robots” , in Proc. IEEE Conference on Industrial Electronics and Applications (ICIEA 2008), pp. 1240-1245, June 2008.

  19. Y. Cao, T. Wang, Y. Chen, H. Wei, B. Wang, Z. Shao, “A New High-Speed Control Algorithm Using Look-Ahead Strategy in CNC System” , in Proc. IEEE Conference on Industrial Electronics and Applications (ICIEA 2008), pp. 372-377, June 2008.

  20. T. Wang, B. Wang, H. Wei, Y. Cao, M. Wang, Z. Shao, “Staying-Alive and Energy-Efficient Path Planning for Mobile Robots”, in Proc. 2008 American Control Conference (ACC 2008), pp. 868-873, June 2008.                                          .

  21. T. Wang, Y. Cao, Y. Chen, H. Wei, B. Wang, Z. Shao, “A New Feedrate Adaptation Control NURBS Interpolation Based on de Boor Algorithm in CNC Systems”, in Proc. 2008 American Control Conference (ACC 2008), pp. 4075-4080, June 2008.

  22. K. Sun, H. Wei, T. Wang, M. Wang, Z. Shao, H. Liu, "MPSOC Architectural Design and Synthesis For Real-Time Biomedical Signal Processing in Gamma Cameras", Proc. 2008 International Conference on Biomedical Electronics and Devices (BIODEVICES 2008), Madeira, Portugal, pp.279-284, Jan. 2008.

  23. M. Liu,  Z. Shao, M. Wang, H. Wei, T. Wang, "Implementing Hybrid Operating Systems with Two-Level Hardware Interrupts", The 28th IEEE Real-Time Systems Symposium (RTSS 2007), pp.244-253, December 3-6, 2007, Tucson, Arizona, USA.

  24. G. Hua, M. Wang, Z. Shao, H. Liu, C. Xue, "Real-Time Loop Scheduling with Energy Optimization via DVS and ABB for Multi-Core Embedded Systems", Proc. 2007 IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2007), pp. 1-12, Taipei, Taiwan, Dec. 2007.

  25. C. Xue, Z. Shao, M. Liu, Q. Zhuge, E. Sha, "Parallel Network Intrusion Detection on Reconfigurable Platform", Proc. 2007 IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2007), pp. 75-86, Taipei, Taiwan, Dec. 2007.

  26. T. Wang,  K. Sun, H. Wei, M. Wang, Z. Shao, H. Liu, "Interconnection Synthesis of MPSoC Architecture for Gamma Camera", Proc. 2007 IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2007), pp. 209-218, Taipei, Taiwan, Dec. 2007.

  27. M. Wang, Z. Shao, C. Xue, E. H.-M. Sha, “Real-Time Loop Scheduling with Leakage Energy Minimization for Embedded VLIW DSP Processors”, The 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp. 12-19, August 21-24, 2007, Daegu, Korea. (Invited Paper).

  28. M. Qiu, C. Xue, Z.Shao, and E. H.-M. Sha, "Energy Minimization with Soft Real-time and DVS for Uniprocessor and Multiprocessor Embedded Systems", in IEEE/ACM Design, Automation and Test in Europe (DATE) , Acropolis, Nice, France, April 16-20, 2007.

  29. M. Qiu, Z. Jia, Z. Shao, C. Xue and E. H.-M. Sha, “Loop Scheduling to Minimize Cost with Data Mining and Prefetching for Heterogeneous DSP,” in Proc. The 18th IASTED International Conference on Parallel and Distributed Computing and Systems (IASTED PDCS), pp. 190-195, Dallas, Texas, Nov. 2006.

  30. M. Qiu, C. Xue, Q. Zhuge, Z. Shao, M. Liu and E. H.-M. Sha, “Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability,” in Proc. IEEE 17th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), pp. 178-181, Steamboat Springs, Colorado, Sept. 2006.

  31. C. Xue, Z. Shao, M. Liu, M. Qiu and E. H.-M. Sha, “Loop Striping: Maximizing Parallelism for Nested Loops,” Proc. 2006 IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2006), pp. 405-414, Seoul, Korea, August, 2006.

  32. B. Xiao, J. Yu, Z. Shao, M. Li, “ Distributed Proximity-Aware Peer Clustering in BitTorrent-like Peer-to-Peer Networks”, Proc. 2006 IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2006), Seoul, Korea, pp. 375-384, August, 2006.

  33. M. Qiu, C. Xue, Z. Shao, Q. Zhuge, M. Liu and E. H.-M. Sha, “Efficient Algorithm of Energy Minimization for Heterogeneous Wireless Sensor Network,” Proc. 2006 IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2006), pp. 25-34, Seoul, Korea, August, 2006.

  34. M. Qiu, Z. Shao, Q. Zhuge, C. Xue, M. Liu and E. H.-M. Sha, “Efficient Assignment with Guaranteed Probability for Heterogeneous Parallel DSP,” Proc. The 12th IEEE International Conference on Parallel and Distributed Systems (ICPADS 2006), Minneapolis, MN, July 2006, pp. 623 - 630.

  35. C. Xue, Z. Shao, M. Liu, M. Qiu, E. H.-M. Sha, “Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture,” Proc. The 12th IEEE International Conference on Parallel and Distributed Systems (ICPADS 2006), Minneapolis, MN, July 2006, pp. 375-382.

  36. M. Liu, Q. Zhuge, Z. Shao, C. Xue and E. H.-M. Sha, “Maximum Loop Distribution and Fusion for Two-level Loops Considering Code Size,” Proc. The 8th International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN 2005), pp. 126-131, Las Vegas, Nevada, Dec. 2005.

  37. C. Xue, Z. Shao, M. Liu, M. Qiu and E. H.-M. Sha, “Optimizing Nested Loops with Iterational and Instructional Retiming,” Proc. The 2005 IFIP International Conference on Embedded and Ubiquitous Computing (EUC-05), pp. 164-173, Nagasaki, Japan, Dec. 2005.

  38. M. Liu, Q. Zhuge, Z. Shao, C. Xue, M. Qiu and E. H.-M. Sha, “Loop Distribution and Fusion Considering Timing and Code Size for Embedded DSP,” Proc. The 2005 IFIP International Conference on Embedded and Ubiquitous Computing (EUC-05), pp. 121-130, Nagasaki, Japan, Dec. 2005.

  39. M. Qiu, M. Liu, C. Xue, Z. Shao, Q. Zhuge and E. H.-M. Sha, “Optimal Assignment with Guaranteed Confidence Probability for Trees on Heterogeneous DSP Systems,” Proc. The 17th IASTED International Conference on Parallel and Distributed Computing Systems, pp. 295-300, Phoenix, Arizona, Nov. 2005.

  40. C. Xue, Z. Shao, M. Liu and E. H.-M. Sha, “Iterational Retiming: Maximize Iteration-Level Parallelism for Nested Loops,” Proc. The 2005 ACM/IEEE/IFIP International Conference on Hardware - Software Codesign and System Synthesis (ISSS-CODES'05), pp. 309-314, New York, New York, Sept. 2005.

  41. M. Liu, Z. Shao, C. Xue, K. Chen, E. H.-M. Sha, “Multi-level Loop Fusion with Minimal Code Size,” Proc. The 18th International Conference on Parallel and Distributed Computing Systems (ISCA PDCS 2005), pp. 185-190, Las Vegas, Sept. 2005.

  42. Y. Chen,  Z. Shao,  Q. Zhuge, C. Xue, B. Xiao and E. H.-M. Sha, “Minimizing Energy via Loop Scheduling and DVS for Multi-Core Embedded Systems,” Proc. The IEEE/IFIP International Workshop on Parallel and Distributed EMbedded Systems (PDES 2005), in conjunction with ICAPDS 2005, Fukuoka, Japan, pp. 2-6 (the best paper award), July 2005.

  43. Z. Shao, C. Xue, Q. Zhuge, E. H.-M. Sha and B. Xiao, “Efficient Array & Pointer Bound Checking Against Buffer Overflow Attacks via Hardware/Software”, Proc. IEEE International Conference on Information Technology (ITCC 05), Information Assurance and Security Track , Las Vegas, NV, April 2005, pp. 780-785.

  44. C. Xue, Z. Shao, Y. Chen and E. H.-M. Sha, “Optimizing DSP Scheduling via Address Assignment with Array and Loop Transformation”, in Proc. 2005 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2005), Philadelphia, PA, March 2005, pp. 85-88 (the best student paper award).

  45. Z. Shao, Q. Zhuge, C. Xue, B. Xiao and E. H.-M. Sha, “High-level Synthesis for DSP Applications using Heterogeneous Functional Units”, in Proc. IEEE Asia and South Pacific Design Automation Conference (ASP DAC 2005), Shanghai, China, Jan. 2005, pp. 302-304.

  46. Z. Shao, Q. Zhuge, M. Liu, B. Xiao and E. H.-M. Sha, “Switching-Activity Minimization on Instruction-level Loop Scheduling for VLIW DSP Applications,” in Proc. IEEE 15th International Conference on Application-specific Systems, Architectures and Processors (ASAP 2004), pp. 224-234, Galveston, Texas, September 2004, pp. 224-234.

  47. M. Liu, Q. Zhuge, Z. Shao and E. H.-M. Sha, “General Loop Fusion Technique for Nested Loops Considering Timing and Code Size,” in Proc. ACM/IEEE International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES 2004), pp. 190-201, Washington DC, September 2004.

  48. B. Xiao, J. Cao, Q. Zhuge, Z. Shao and E. H.-M. Sha, “Shortest Path Tree Update for Multiple Link State Decrements,” in Proc. IEEE Global Telecommunications Conference (Globecom 2004), Dallas, Texas, November, 2004.

  49. M. Liu, Q. Zhuge, Z. Shao, K. Chen and E. H.-M. Sha, “Loop Fusion via Retiming for DSP Applications,” in Proc. 17th International Conference on Parallel and Distributed Computing Systems (ISCA PDCS), pp. 403-408, San Francisco , California, September, 2004.

  50. Z. Shao, Q. Zhuge, M. Liu, E. H.-M. Sha and B. Xiao, “Loop Scheduling for Real-Time DSPs with Minimum Switching Activities on Multiple-functional-unit Architectures,” in Proc. The 2004 International Conference on Embedded And Ubiquitous Computing (EUC 2004), pp. 53-63, LNCS, Springer, Aizu-Wakamatsu City, Japan, August, 2004.

  51. Q. Zhuge, Z. Shao, and E. H.-M. Sha, “Timing Optimization of Nested Loops Considering Code Size for DSP Applications,“ in  Proc. The 2004 International Conference on Parallel Processing (ICPP 2004), pp. 475-482, Montreal, Quebec, Canada, August 2004.

  52. X. Chun, Z. Shao, E. H.-M. Sha and B. Xiao, “Optimizing Address Assignment for Scheduling Embedded DSPs,” in Proc. The 2004 International Conference on Embedded And Ubiquitous Computing (EUC 2004),, pp. 64-73, LNCS, Springer, Aizu-Wakamatsu City, Japan, August, 2004.

  53. B. Xiao, J. Cao, Q. Zhuge, Z. Shao, and E. H.-M. Sha, “Dynamic Update of SPT in OSPF,” in Proc. 2004 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN 2004), pp. 18-23, Hong Kong, May, 2004.

  54. Z. Shao, Q. Zhuge, Y. He, C. Xue, M. Liu and E. H.-M. Sha, “Assignment and Scheduling of Real-time DSP Applications for Heterogeneous Functional Units,” in 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM Proceeding, Santa Fe, Apr. 2004.

  55. Z. Shao, C. Xue, Q. Zhuge, E. H.-M. Sha and B. Xiao,” Security Protection and Checking in Embedded System Integration Against Buffer Overflow Attacks,” In Proc. Information Assurance and Security special track in conjunction with International Conference on Information Technology: Coding and Computing (ITCC 2004), Volume I, pp. 409-413, Las Vegas, Apr. 2004.

  56. Z. Shao, Q. Zhuge, Y. He and E. H.-M. Sha, “Defending Embedded Systems Against Buffer Overflow via Hardware/Software,” in Proc. IEEE 19th Annual Computer Security Applications Conference (ACSAC 2003), pp. 352-361, Las Vegas, Dec. 2003.

  57. Y. He, Z. Shao, B. Xiao, Q. Zhuge and E. Sha, “Reliability Driven Task Scheduling for Tightly Coupled Heterogeneous Systems,” in Proc. IASTED International Conference on Parallel and Distributed Computing and Systems (IASTED PDCS), pp. 465-470, Marina Del Ray, CA, Nov. 2003.

  58. B. Xiao, Q. Zhuge, Y. He, Z. Shao and E. Sha, “Algorithms for Disk Covering Problems with the Most Points,” in Proc. IASTED International Conference on Parallel and Distributed Computing and Systems (IASTED PDCS), pp. 541-546, Marina Del Ray, CA, Nov. 2003.

  59. Q. Zhuge, Z. Shao, B. Xiao and E. H.-M. Sha, “Design Space Minimization with Timing and Code Size Optimization for Embedded DSP,” in Proc. IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2003), pp. 144-149, Newport Beach, California, Oct. 2003. (Nominated for the best paper as one of the final four).

  60. Z. Shao, Q. Zhuge, Y. Zhang and E. H.-M. Sha, “Efficient Scheduling for Low-Power High-Performance DSP Applications,” in Proc. The 2nd Workshop on Hardware/Software Support for High Performance Scientific and Engineering Computing in conjunction with The 12th International Conference on Parallel Architecture and Compilation Techniques (PACT 2003), pp. 135-149, New Orleans, Louisiana, Sept. 2003.

  61. B. Xiao, Q. Zhuge, Z. Shao and E. H.-M. Sha, “Design and analysis of improved shortest path tree update for network routing,” in Proc. ISCA 16th International Conference on Parallel and Distributed Computing Systems (ISCA PDCS), pp. 82-87, Reno, Nevada, August 2003.

  62. Z. Shao, Q. Zhuge, E. H.-M. Sha and C. Chantrapornchai, “Loop Scheduling for Minimizing Schedule Length and Switching Activities,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS 2003), Bangkok, vol. V,  pp. 109-112, Thailand, May 2003.

  63. Q. Zhuge, B. Xiao, Z. Shao, E. H.-M. Sha and C. Chantrapornchai, “Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops,” in Proc. ACM International Symposium on System Synthesis (ISSS 2002), pp. 144-149, Kyoto, Japan, Nov. 2002.

  64. Q. Zhuge, Z. Shao and E. H.-M. Sha, “Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications,” in Proc. International Conference on Parallel Processing (ICPP 2002), pp. 613-620, Vancouver, Canada, August 2002.

  65. Z. Shao, Q. Zhuge, E. H.-M. Sha and C. Chantrapornchai, “Analysis And Algorithms For Scheduling With Minimal Switching Activities,” in Proc. IEEE Midwest Symposium on Circuits and Systems (MWCAS 2002), Vol. I, pp. 372-375, Tulsa, Oklahoma, August 2002.